39 # error "F_CPU is undefined"
47 #include <avr/sleep.h>
48 #include <avr/interrupt.h>
49 #include <util/delay.h>
50 #include <avr/pgmspace.h>
51 #include <avr/eeprom.h>
52 #include <util/crc16.h>
54 #include "board_cfg.h"
68 #define MCU_IRQ_ENABLE sei
75 #define MCU_IRQ_DISABLE cli
89 #define DELAY_US(x) _delay_ms(x/1000.0)
93 #define DELAY_MS(x) _delay_ms(x)
99 # define PULLUP_KEYS (0)
106 #define SLEEP_ON_IDLE()\
108 set_sleep_mode(SLEEP_MODE_IDLE);\
116 # define TIMER_POOL_SIZE (0)
117 # define TIMER_INIT() do{}while(0)
118 # define TIMER_IRQ TIMER1_OVF_vect
121 #ifndef HIF_DEFAULT_BAUDRATE
122 # define HIF_DEFAULT_BAUDRATE (9600)
128 # define HIF_TYPE (HIF_NONE)
131 #ifndef HIF_IO_ENABLE
133 # define HIF_IO_ENABLE() do{}while(0)
136 #define HIF_TYPE_IS_NONE (HIF_TYPE == HIF_NONE)
137 #define HIF_TYPE_IS_UART ((HIF_TYPE >= HIF_UART_0) && ( HIF_TYPE <= HIF_USARTE0))
138 #define HIF_TYPE_IS_USB ((HIF_TYPE == HIF_FT245) || (HIF_TYPE == HIF_AT90USB))
140 #ifndef DEFAULT_SPI_RATE
147 # define DEFAULT_SPI_RATE (SPI_RATE_1_2)
151 #ifndef TRX_RESET_INIT
153 # define TRX_RESET_INIT() DDR_TRX_RESET |= MASK_TRX_RESET
156 #ifndef TRX_RESET_HIGH
158 # define TRX_RESET_HIGH() PORT_TRX_RESET |= MASK_TRX_RESET
161 #ifndef TRX_RESET_LOW
163 # define TRX_RESET_LOW() PORT_TRX_RESET &= ~MASK_TRX_RESET
166 #ifndef TRX_SLPTR_INIT
168 # define TRX_SLPTR_INIT() DDR_TRX_SLPTR |= MASK_TRX_SLPTR
171 #ifndef TRX_SLPTR_HIGH
173 # define TRX_SLPTR_HIGH() PORT_TRX_SLPTR |= MASK_TRX_SLPTR
176 #ifndef TRX_SLPTR_LOW
178 # define TRX_SLPTR_LOW() PORT_TRX_SLPTR &= ~MASK_TRX_SLPTR
181 #if ! defined(DI_TRX_IRQ) && ! defined(EI_TRX_IRQ)
183 # define DI_TRX_IRQ disable_all_trx_irqs
184 # define EI_TRX_IRQ enable_all_trx_irqs
187 #if ! defined(ACK_TRX_IRQ)
188 # define ACK_TRX_IRQ() do{}while(0)
191 #if defined (DBG_PORT) && defined (DBG_DDR) && defined (DBG_PIN)
192 # define DBG_INIT() do{DBG_DDR |= DBG_PIN; DBG_PORT &= ~DBG_PIN;}while(0)
193 # define DBG_SET() do{DBG_PORT |= DBG_PIN;}while(0)
194 # define DBG_CLR() do{DBG_PORT &= ~DBG_PIN;}while(0)
195 # define DBG_TOGGLE() do{DBG_PORT ^= DBG_PIN;}while(0)
197 # define DBG_INIT() do{}while(0)
198 # define DBG_SET() do{}while(0)
199 # define DBG_CLR() do{}while(0)
200 # define DBG_TOGGLE() do{}while(0)
205 #if ! defined(NO_KEYS) && 0 == 1
206 # define WIBO_FLAVOUR_KEYPRESS (1)
207 # define WIBO_FLAVOUR_KEYPRESS_KEYNB (0)
210 #if defined(GPIOR0) && 0 == 1
211 # define WIBO_FLAVOUR_MAILBOX (1)
212 # define WIBO_FLAVOUR_MAILBOX_REGISTER (GPIOR0)
213 # define WIBO_FLAVOUR_MAILBOX_CODE (0xA5)
216 #if defined(WIBO_FLAVOUR_MAILBOX)
217 # define WIBO_MAILBOX_SET() \
218 do{WIBO_FLAVOUR_MAILBOX_REGISTER = WIBO_FLAVOUR_MAILBOX_CODE;}while(0);
219 # define WIBO_MAILBOX_CLR() \
220 do{WIBO_FLAVOUR_MAILBOX_REGISTER = ~WIBO_FLAVOUR_MAILBOX_CODE;}while(0);
244 uint8_t _reserved_[2];
261 uint8_t *pram = (uint8_t*)ncfg;
262 uint8_t crc = 0, zcnt = 0;
265 #if FLASHEND > 0xffffL
266 *pram = pgm_read_byte_far(((
long)FLASHEND - i + 1));
268 *pram = pgm_read_byte_near((FLASHEND - i + 1));
271 crc = _crc_ibutton_update(crc, *pram);
272 zcnt += *pram ? 0 : 1;
299 uint8_t *pram = (uint8_t*)ncfg;
300 uint8_t crc = 0, zcnt = 0;
303 *pram = eeprom_read_byte( (
const uint8_t *) offset++ );
304 crc = _crc_ibutton_update(crc, *pram);
305 zcnt += *pram ? 0 : 1;
328 uint8_t *pram = (uint8_t*)ncfg;
332 eeprom_write_byte( (uint8_t *)offset++, *pram );
333 crc = _crc_ibutton_update(crc, *pram++);
336 eeprom_write_byte((uint8_t *)offset, crc );
344 typedef void (*func_ptr_t)(void) __attribute__((noreturn));
345 const func_ptr_t jmp_boot = (func_ptr_t) BOOTLOADER_ADDRESS;
346 #if defined(WIBO_FLAVOUR_MAILBOX)
353 #if defined(__AVR_XMEGA__)
355 #if F_CPU == 4000000UL
356 #define CLK_PSADIV (CLK_PSADIV_8_gc)
357 #elif F_CPU == 8000000UL
358 #define CLK_PSADIV (CLK_PSADIV_4_gc)
359 #elif F_CPU == 16000000UL
360 #define CLK_PSADIV (CLK_PSADIV_2_gc)
361 #elif F_CPU == 32000000UL
362 #define CLK_PSADIV (CLK_PSADIV_1_gc)
364 #error F_CPU frequency not supported
373 static inline void atxmega_switch_clock(
void)
375 OSC.CTRL |= OSC_RC32MEN_bm;
376 while (!(OSC.STATUS & OSC_RC32MRDY_bm));
379 CLK.PSCTRL = CLK_PSADIV | CLK_PSBCDIV_1_1_gc;
382 __asm__
volatile (
"nop");
385 CLK.CTRL = CLK_SCLKSEL_RC32M_gc;
398 #if defined(__AVR_XMEGA__)
399 atxmega_switch_clock();
402 #ifdef CHECKBOOTLOADER
static void store_node_config_eeprom(node_config_t *ncfg, uint8_t *offset)
static void mcu_init(void)
static void jump_to_bootloader(void)
#define MCU_IRQ_DISABLE
Enable interrupts globally.
static uint8_t get_node_config_eeprom(node_config_t *ncfg, uint8_t *offset)
static uint8_t get_node_config(node_config_t *ncfg)